A continuing goal of the semiconductor industry has been to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as non-volatile memory devices (e.g., NAND Flash memory devices). One way of increasing memory density in non-volatile memory devices is to utilize vertical memory array (also referred to as a “three-dimensional (3D) memory array”) architectures. A conventional vertical memory array includes semiconductor pillars extending through openings in tiers of conductive structures (e.g., word line plates, control gate plates, access lines, word lines) and dielectric materials at each junction of the semiconductor pillars and the conductive structures. Such a configuration permits a greater number of transistors to be located in a unit of die area by building the array upwards (e.g., vertically) on a die, as compared to structures with conventional planar (e.g., two-dimensional) arrangements of transistors.
Conventional vertical memory arrays include tiers of conductive structures (e.g., access lines, word lines) separated by dielectric materials. One such vertical memory array is a so-called “MONOS” type memory array, which stands for metal-oxide-nitride-oxide-semiconductor, referring to the materials forming each individual memory cell. Conventional MONOS type memory arrays may be formed by forming the semiconductor pillars through a stack of alternating first and second dielectric materials, forming slots through the stack adjacent to the semiconductor pillars, removing the second dielectric materials through the slots, and replacing the second dielectric materials with a conductive material to form word line plates. During such a process, all or substantially all of the second dielectric material is replaced by the conductive material, such that a body of the vertical memory array includes alternating layers of the first dielectric material and the conductive word line plates.
Some conventional vertical memory arrays include so-called “through-array vias,” which are conductive vias that extend through the vertical memory array to a sub-array feature. Through-array vias potentially reduce an area that the vertical memory array and associated circuitry covers on a semiconductor device, compared to vias or other contacts that are formed outside of an area of the vertical memory array. However, the formation of the through-array vias requires additional processing acts and cost. For example, to conventionally form such through-array vias that are electrically isolated from the conductive word line materials, a portion of the alternating layers of the first dielectric material and the conductive word line material is removed and replaced with a dielectric material, through which the through-array vias are formed.
It would, therefore, be desirable to develop improved structures and methods of forming vertical memory arrays with through-array vias for semiconductor devices (e.g., vertical memory devices, such as NAND Flash memory devices) that reduce the number and complexity of additional processing acts practiced in conventional methods and structures.